The subject matter relates to an internal voltage generating circuit of a semiconductor memory device, and more particularly, to a high-voltage generating circuit for boosting a supply voltage to generate a high voltage used in a semiconductor device.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses received from a data processor.
As the integration density of semiconductor memory devices has increased, circuits are designed based on a sub-micron design rule. Thus, circuit components of the semiconductor memory devices have become ultra-fine. Meanwhile, as the operating frequency of the CPU increases, semiconductor memory devices within systems are also designed to operate in high frequency environments. In order to achieve high frequency operation while components are becoming ultra-fine, a power supply voltage should be lowered. For example, a power supply voltage lower than 1.5 V is applied to synchronous memory devices, such as double data rate version 3 (DDR3) or higher version, which are considered current and next generation memory devices.
As the power supply voltage for the next generation memory device is lowered, internal voltages with different voltage levels than the power supply voltage are required to support various operations inside electronic devices and semiconductor memory devices. It is difficult and inefficient to receive all of the internal voltages from external circuits. Therefore, the semiconductor memory devices include internal voltage generating circuits. Generally, such an internal voltage generating circuit generates an internal voltage according to a level of an external power supply voltage. For example, an internal voltage generating circuit may generate an internal voltage having the same level as the input power supply voltage, or may generate an internal voltage having a different level from the input power supply voltage, such as one half, one quarter, or double the input power supply voltage.
Among the internal voltage generating circuits, on-chip high voltage generating circuits have become more important. A high voltage generating circuit is a circuit for generating a high voltage higher than a power supply voltage. The high voltage generating circuit is used for driving word lines (WL) connected to unit cells of the semiconductor memory device. Also, the high voltage generating circuit is used to generate a driving power for a data output buffer.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a reference voltage generator 110, a high voltage detector 120, a high voltage oscillator 130, a high voltage generator 140, and a cell transistor 150. The cell transistor 150 is included in a unit cell for storing data. The cell transistor 150 is connected to a word line and acts as a switch to output data stored in the unit cell or store data in the unit cell. The semiconductor memory device needs internal voltages having various levels for various internal operations. Although the high voltage is used in various internal circuits of the semiconductor memory device, a representative case will be described below.
After an external power supply voltage VDD is applied, the high voltage detector 120 detects a high voltage VPP generated by the high voltage generator 140 and outputs a high voltage enable signal VPPE for enabling the high voltage generator 140 if the detected high voltage VPP does not reach a predetermined level. The high voltage oscillator 130 outputs control pulses P1 and P2 having a constant period in response to the high voltage enable signal VPPE, and the high voltage generator 140 generates a high voltage VPP in response to the control pulses P1 and P2. In addition, the reference voltage generator 110 generates a reference voltage VREF having a stable level to the high voltage detector 120. The high voltage detector 120 receives the reference voltage VREF and determines if the high voltage VPP output from the high voltage generator 140 is higher than a threshold based on reference voltage VREF.
More specifically, the reference voltage generator 110 is a basic circuit in the internal voltage generating circuit of the semiconductor memory device and generates the reference voltage VREF having a stable level (e.g., 0.8 V). The reference voltage VREF is input to the high voltage detector 120. The high voltage detector 120 receives the reference voltage VREF and the high voltage VPP, and outputs the high voltage enable signal VPPE. More specifically, the high voltage detector 120 divides the high voltage VPP and compares the divided high voltage with the reference voltage VREF. When the divided high voltage is higher than the reference voltage VREF, the high voltage detector 120 outputs the high voltage enable signal VPPE at a logic low level to disable the high voltage oscillator 130. When the divided high voltage is lower than the reference voltage VREF, the high voltage detector 120 outputs the high voltage enable signal VPPE at a logic high level to enable the high voltage oscillator 130.
The high voltage oscillator 130 receives the high voltage enable signal VPPE from the high voltage detector 120. The high voltage oscillator 130 is disabled when the high voltage enable signal VPPE is at a logic low level. That is, the first control signal P1 output from the high voltage oscillator 130 is locked to a logic low level. At this point, the second control signal P2 is locked to a logic high level. Alternatively, when the high voltage enable signal VPPE output from the high voltage detector 120 is at a logic high level, the high voltage oscillator 130 is enabled to output the first and second control signals P1 and P2 having a pulse form with a constant period.
The high voltage generator 140, receiving the first and second control signals P1 and P2 having the pulse form with the constant period, receives an external power supply voltage VDD and operates internal pumping capacitors to increase the level of the high voltage VPP. When the first control signal P1 does not have a pulse form with constant period, but is locked to a logic low level, the high voltage generator 140 does not operate internal pumping capacitors to increase the level of the high voltage VPP. Consequently, when the level of the high voltage VPP is low, the high voltage detector 120, the high voltage oscillator 130, and the high voltage generator 140 operate to boost the power supply voltage VDD by the pumping capacitor of the high voltage generator 140, thereby increasing the level of the high voltage VPP.
FIG. 2 is a circuit diagram of the high voltage generator 140 of FIG. 1.
Referring to FIG. 2, the high voltage generator 140 includes inverters 142A and 142B for inverting the control signals P1 and P2 output from the high voltage oscillator 130, pumping capacitors C0 and C1 for performing a boosting operation, and a high voltage output unit 144 for outputting the high voltage VPP generated based on the power supply voltage VDD. Specifically, the high voltage output unit 144 includes first and second MOS transistors M1 and M2 for transferring the high voltage VPP, and third to fifth transistors M3 to M5 acting as a current source for a boosting operation.
Upon operation of the high voltage generator 140, an initial VPP output node is reset to a level of VDD−Vt by the applied power supply voltage VDD. In addition, nodes R1 and R2 are also initialized to a level of VDD−Vt by the applied power supply voltage VDD. To simplify the discussion, it is assumed that the VPP output node and the nodes R1 and R2 are reset to a level of the power supply voltage VDD, without considering the threshold voltage (Vt) of the transistor.
When the first control signal P1 changes from the logic high level to the logic low level, an output node A1 of the inverter 142A changes from a logic low level to a logic high level. At this point, the level of the node R1 rises from the initial power supply voltage VDD to two times the power supply voltage, 2×VDD, by the operation of the pumping capacitor C0. Due to the second control signal P2 having a phase opposite to the first control signal, the node R2 is kept at the level of the initial power supply voltage VDD. Hence, the first MOS transistor M1 is turned on and two times the power supply voltage, 2×VDD, is transferred to the VPP output node.
Likewise, when the second control signal P2 changes from the logic high level to the logic low level, the output node A2 of the inverter changes from a logic low level to a logic high level. At this point, the level of the node R2 rises from the power supply voltage VDD to two times the power supply voltage, 2×VDD, by the operation of the pumping capacitor C1. Since the first control signal P1 has a phase opposite to the second control signal P2, the node B1 falls from two times the power supply voltage 2×VDD to the power supply voltage VDD. Hence, the second MOS transistor M2 is turned on and two times the power supply voltage 2×VDD is transferred to the VPP output node.
FIG. 3 is a graph depicting the operation of the semiconductor memory device of FIG. 1.
The generation of the high voltage VPP after the power supply voltage VDD is applied is shown in FIG. 3. In the initial operation of the semiconductor memory device, the power supply voltage rises from a low level to a target level. The pumping capacitor repetitively boosts the power supply voltage VDD and the high voltage VPP rises from an initial low level to a VPP target level. That is, the high voltage VPP rises up to the VPP target voltage while the VPP output node of the semiconductor memory device is charged by the continuous pumping operation.
The pumping capacitors C0 and C1 having the relationship of Q=CV have relatively smaller capacitances than those of various loads connected to the VPP output node within the semiconductor memory device. Therefore, several pumping operations must be performed in order to increase the level of the VPP output node up to the VPP target level. However, the actual operation of the semiconductor memory device cannot wait a long time for the high voltage VPP to be charged up to the VPP target level after the input of the power supply voltage VDD.
Hence, the pumping capacitors C0 and C1 must have large capacitances in order to increase the high voltage VPP up to the target voltage level within a predetermined time. Accordingly, the capacitors C0 and C1 must be designed with large sizes. Consequently, a total size of the semiconductor memory device increases, which negatively affects the design of the high-integrated semiconductor memory device.